As a conventional successive approximation A/D converter, for example, there is a successive approximation A/D converter disclosed in Non-Patent Document 1. This successive approximation A/D converter A/D converts an analog input signal Ain into an n-bit digital output signal Vout (where n is a natural number of 3 or more).
FIG. 7 is a circuit configuration diagram for describing a conventional successive approximation A/D converter shown in Patent Document 3 (see FIG. 5).
As shown in FIG. 7, one capacitor 506_1 whose capacitance value is set to a predetermined reference capacitance C is provided in this successive approximation A/D converter. Further, (n−2) capacitors 506_2 to 506_(n−1), each of which is set to have each of capacitances C/2 to C/2 (n−2) obtained by weighting the above reference capacitance C with the reciprocals of powers of 2 in a step-by-step manner, are also provided. Further, one capacitor 506—n whose capacitance is set to be C/2(n−2) obtained by weighting the reference capacitance C with 1/2(n−2) like the above capacitor 506_(n−1) is provided.
A capacitor array 506 is composed of the above multiple capacitors 506_1 to 506—n, and a holding voltage on a corresponding capacitor of the capacitors in this capacitor array 506 is selectively applied sequentially to make a successive comparison between the analog input signal Ain and the reference voltage to be described later.
The right ends of the capacitors 506_1 to 506_(n−1) and the capacitor 506—n are connected to a storage node (SN in FIG. 7) capable of storing electric charge. The left ends of the capacitors 506_1 to 506_(n−1) are connected to terminals O of switch groups 505_1, 505_2 to 505_(n−1), respectively.
Each of the switch groups 505_1, 505_2 to 505_(n−1) has a terminal O common to the respective switch groups and individual terminals C, P, and N corresponding to the terminal O. When a switch 503d—k (where k is a natural number of 1 to (n−1)) is turned on by a control signal CTRL from a controller 501, a short circuit is made between the terminal C and the terminal O.
When a switch 503e—k is turned on, a short circuit is made between the terminal P and the terminal O, while when a switch 503f—k is turned on, a short circuit is made between the terminal N and the terminal O. Note that two or more of the switch 503d—k, the switch 503e—k, and the switch 503f—k are never turned on at the same time.
The terminals C of the switch groups 505_1 to 505_(n−1) and the left end of the capacitor 506—n are connected to the switch 503b and the switch 503c. Then, when the switch 503c is turned on, the terminals C of the switch groups 505_1 to 505_(n−1) and the left end of the capacitor 506—n are coupled to an input node (Ain in FIG. 7).
Further, when the switch 503b is turned on, the terminals C of the switch groups 505_1 to 505_(n−1) and the left end of the capacitor 506—n are coupled to a node of an analog common voltage VC as the reference voltage to be described later.
The terminals P of the switch groups 505_1 to 505_(n−1) are coupled to a node of a positive full-scale reference voltage VRP based on the analog common voltage VC, and the terminals N of the switch groups 505_1 to 505_(n−1) are coupled to a node of a negative full-scale reference voltage VRN based on VC.
The right ends of the capacitors 506_1 to 506_(n−1) and the right end of the capacitor 506—n are connected to a switch 503a and the inverting input terminal of a comparator 504 through the storage node SN. When the switch 503a is turned on, the storage node SN is coupled to the node of the analog common voltage VC. Further, a judging signal DO from the comparator 504 is input into the controller 501 and an output register 502.
The controller 501 is composed of a combinational circuit (logic circuit) and the like, and outputs a control signal CTRL to control switching among the switch groups 505_1 to 505_(n−1) and the switches 503a to 503c. 
In other words, the controller 501 generates a control signal CTRL based on the judging signal DO to switch among the switch groups 505_1 to 505_(n−1) sequentially in order to obtain an internal voltage (voltage of the storage node SN) corresponding to the analog input signal Ain.
Further, a trigger clock CLK generated by the controller 501 is supplied to the comparator 504. In synchronization with this trigger clock CLK, the comparator 504 judges a magnitude relationship between the voltage of the storage node SN and the reference voltage VC. When SN<VC, DO=H(1) is output, while when SN>VC, DO=L(0) is output.
The trigger clock CLK from the controller 501 is also supplied to the output register 502, and the judging signal DO is supplied from the comparator 504 to this output register 502.
In synchronization with the trigger clock CLK, the output register 502 holds DN=1 (where N is a natural number of 1 to n) when the judging signal DO=1 from the comparator 504, or holds DN=0 when the judging signal DO=0.
After receiving judging signals D1 to Dn as n output values from the comparator 504, D1 to Dn held as mentioned above are output as a digital output signal Vout from the output register 502.
FIGS. 8A to 8D are charts for describing the operation of the successive approximation A/D converter when the number of bits is six in FIG. 7.
FIG. 8A is a chart showing an example of plotting voltage as judged voltage having an inverted polarity of the voltage of the storage node SN, representing voltage on the ordinate and time on the abscissa. FIG. 8B is a chart showing an example of changes in trigger clock CLK output from the controller 501, representing the judgment timings of the comparator 504 at regular intervals. FIG. 8C is a chart showing an example of values of the judging signal DO of the comparator 504. FIG. 8D is a chart showing an example of a digital output signal Vout output based on the upper 6 bits of judgment results D1 to D6.
Further, FIGS. 8A to 8D represent, as an example, a case where VRP−VC=VC−VRN=VR is assumed, and under this condition, the analog input voltage Ain of an analog input signal where Ain=(10·8/16)×VR is sampled.
As the initial state, when the voltage of the capacitors 506_1 to 506—n follows the analog input voltage Ain, the switch 503a and the switch 503c are on, and the switch 503b is off. Further, in the switch groups, the switches 503d_1 to 503d_(n−1) are on, the switches 503e_1 to 503e_(n−1) and the switches 503f_1 to 503f_(n−1) are off.
At the time of sampling (discretizing) the analog input voltage Ain through the capacitors 506_1 to 506—n, the switch 503a is turned off by the control signal CTRL from the controller 501 and the switch 503c is turned off immediately. After that, the switch 503b is turned on to make the polarity of the sampled analog input voltage Ain inverted and appear on the storage node SN as −Ain. Here, a non-overlapping relationship in which the switch 503b and the switch 503c are not turned on at the same time is established.
Suppose that, after switching among the switches 503a, 503b, and 503c as mentioned above, electric charge is sufficiently redistributed with the parasitic capacitance ignored for convenience sake. In this case, a first judgment rising clock in FIG. 8B (timing of “1st Judge” in FIG. 8A) is input to the comparator 504 at a time when the voltage of the storage node SN converges on −Ain sufficiently. In response to the input of this first judgment rising clock, the comparator 504 compares the voltage of the storage node SN with the reference voltage VC.
This comparison at the comparator 504 directly means the comparison between the voltage of the storage node SN and the reference voltage VC, but as will be easily understood from the above-mentioned phenomenon, it can be considered as a comparison of −Ain (therefore, Ain), which uniquely determines the voltage of the storage node SN in a substantial way, with the reference voltage VC.
Therefore, when −Ain<VC, i.e., Ain>VC, DO=1 is output from the comparator 504, while when −Ain>VC, i.e., Ain<VC, DO=0 is output as the first judgment result.
When the first judgment result mentioned above is DO=1, the controller 501 controls the switch group 505_1 to turn the switch 503d_1 off and the switch 503e_1 on. As a result, the already-mentioned positive full-scale reference voltage VRP is applied to the terminal O, i.e., to the left end of the capacitor 506_1. Therefore, the voltage of the storage node SN comes to −(Ain−VR/2) [V] by the redistribution of electric charge.
On the other hand, when the first judgment result is DO=0, the controller 501 controls the switch group 505_1 to turn the switch 503d_1 off and the switch 503f_1 on. As a result, the negative full-scale reference voltage VRN is applied to the terminal O, i.e., to the left end of the capacitor 506_1. Therefore, the voltage of the storage node SN comes to −(Ain+VR/2) [V] by the redistribution of electric charge.
Similarly, the voltage of the storage node SN and the reference voltage VC are compared at a time when the y-th judgment rising clock (where y is a natural number of 2 to (n−1)) is input, and the switch group 505—y is controlled according to this judgment result.
Then, the voltage of the storage node SN and the reference voltage VC are compared at a time when the (n−1)-th judgment rising clock is input, and after the switch group 505_(n−1) is controlled according to the result, the voltage of the storage node SN and the reference voltage VC are compared at a time when the n-th judgment rising clock is input.
As a result of the successive comparison operations of the comparator 504 mentioned above, the successive comparison operations for 1 to n bits are completed, and n-bit output data is output from the output register 502 as a digital output signal Vout.
As an example, FIG. 8A represents transitions of judged signal when voltage of the storage node SN, VSN=−(10.8/16)×VR, is sampled. Since −(10.8/16)×VR<VC at the first judgment rising clock, D1=1 is output as shown in FIG. 8C. As a result, the switch group 505_1 is so controlled that the voltage of the storage node SN will come to VSN=−(10.8/16)×VR+VR/2=−(2.8/16)×VR.
Since −(2.8/16)×VR<VC at the second judgment rising clock in FIG. 8B (timing of “2nd Judge” in FIG. 8A), D2=1 is output as shown in FIG. 8C. As a result, the switch group 505_2 is so controlled that the voltage of the storage node SN will come to VSN=−(2.8/16)×VR+VR/4=(1.2/16)×VR.
After that, the same processing is repeated up to (n−1) times. When Dn is determined by the n-th judgment rising clock to complete the n-bit successive comparison operation, the output register 502 outputs, based on the stored D1 to Dn, n-bit output data as the output signal Vout.
FIG. 8D is a chart showing an example of a digital output signal Vout output based on the upper 6 bits of the judgment results D1 to D6. As shown in FIG. 8C, the upper 6 bits of the judgment results are D1=“1,” D2=“1,” D3=“0,” D4=“1,” D5=“0,” and D6=“1.” As shown in FIG. 8D, the output register 502 arranges these in order from the highest-order bit and outputs the upper 6 bits, “110101,” of the digital output signal Vout. For example, the output register 502 is composed of a shift register and the like.
Like FIGS. 8A to 8D, FIGS. 9A to 9D are charts for describing the operation of the successive approximation A/D converter when the number of bits is six.
As an example, FIG. 9A represents transitions of judged signal when voltage of the storage node SN, VSN=−(10.0/16)×VR, is sampled. Since −(10.0/16)×VR<VC at the first judgment rising clock (timing of “1st Judge” in FIG. 9A), D1=1 is output as shown in FIG. 9C. As a result, the switch group 505_1 is so controlled that the voltage of the storage node SN will come to VSN=−(10.0/16)×VR+VR/2=−(2.0/16)×VR.
Since −(2.0/16)×VR<VC at the second judgment rising clock in FIG. 9B (timing of “2nd Judge” in FIG. 9A), D2=1 is output as shown in FIG. 9C. As a result, the switch group 505_2 is so controlled that the voltage of the storage node SN will comes to VSN=−(2.0/16)×VR+VR/4=(2.0/16)×VR. FIG. 9D is a chart showing an example of the digital output signal Vout output based on the upper 6 bits of the judgment results D1 to D6.    Patent Document 1: JP H02-244823 A    Patent Document 2: JP 2011-061597 A    Patent Document 3: JP 2011-199403 A    Patent Document 4: U.S. Pat. No. 7,834,793    Non-Patent Document 1: Toshikazu Yoneyama, Analog-to-Digital Converter, Ohmsha Ltd. (published in September, 1983), pp. 99-104.